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14 - bit, 170 msps/250 msps, jesd204b, dual analog - to - digital converter data sheet ad9250 rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analo g devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2017 analog devices, inc. all rights reserved. technical support www.analog.com f eatures jesd204b subclass 0 or subclass 1 coded serial digital outputs signal - to - noise ratio ( snr ) = 7 0. 6 dbfs at 185 mhz a in and 250 msps spurious - free dynamic range ( sfdr ) = 8 8 dbc at 185 mhz a in and 250 msps total power con sumption: 711 m w at 250 msps 1.8 v supply voltages integer 1 - to - 8 input clock d ivider sample rates of up to 2 50 msps if sampling frequencies of up to 4 0 0 mhz internal analog - to - digital converter ( adc ) voltage reference flexible analog input range 1 .4 v p - p to 2 .0 v p - p (1.75 v p - p no minal ) adc clock duty cycle stabilizer (dcs) 95 db channel isolation/crosstalk serial port control energy saving power - down modes applications diversity radio systems multimode digital receivers (3g) td - scdma, wim ax , w - cdma, cdma2000, gsm, edge, lte docs is 3.0 cmts upstream receive paths hfc digital reverse path receivers i/q demodulation systems smart antenna systems electronic test and measurement equipment r adar r eceivers comsec radio architectures ied detection/jamming systems general - purpose software radios broadband data applications functional block dia gram cml, tx outputs jesd204b interface high speed serializers pipeline 14-bit adc pipeline 14-bit adc cmos digital input cmos digital output fast detect control registers clock generation avdd vin+a sdio sclk fdb fda pdwn serdout1 serdout0 cs vin?a vin+b vcm vin?b sysref syncinb clk rfclk drvdd dvdd agnd dgnd drgnd cmos digital input/output ad9250 10559-001 rst figure 1. product highlights 1. integrated dual, 14 - bit, 170 msps/ 250 msps adc. 2. the configurable jesd204b output block supports up to 5 gbps per lane. 3. an on - chip , phase - locked loop ( pll ) allows users to provide a single adc sampling clock; the pll multiplies the adc sampling clock to produce the corresponding jesd204b data rate clock . 4. support for an optional rf c lock input to ease system board design. 5. proprietary differen tial input maintains excellent snr performance for input frequencies of up to 4 0 0 mhz. 6. operation from a single 1.8 v power supply. 7. standard serial port interface (spi) that supports various product features and functions such as controlling the clock dcs , power - down, test modes, voltage reference mode, over range fast detection, and serial output configuration. this product may be protected by one or more u.s. or international patents.
ad9250 data sheet rev. e | page 2 of 45 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 p roduct highlights ........................................................................... 1 revision history ............................................................................... 3 general description ......................................................................... 4 specif ications ..................................................................................... 5 adc dc specifications ............................................................... 5 adc ac specifications ............................................................... 6 digital specifications ................................................................... 7 switching specifications .............................................................. 9 timing specifications ................................................................ 10 absolute maximum ratings .......................................................... 11 thermal characteristics ............................................................ 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 14 equivalent circuits ......................................................................... 18 theory of operation ...................................................................... 20 adc architecture ...................................................................... 20 analog input considerations .................................................... 20 voltage reference ....................................................................... 21 clock input considerations ...................................................... 21 power dissipation and sta ndby mode ..................................... 24 digital outputs ............................................................................... 25 jesd204b transmit top level description ............................ 25 jesd204b overview .................................................................. 25 jesd204b synchronization details ......................................... 26 link setup parameters ............................................................... 26 frame and lane alignment monitoring and correction ..... 30 digital outputs and timing ..................................................... 30 adc overrange and gain control .......................................... 32 adc overrange (or) ................................................................ 32 gain switching ............................................................................ 32 dc correction ................................................................................ 33 dc correction bandwidth ........................................................ 33 dc correction readback .......................................................... 33 dc correction freeze ................................................................ 33 dc correction (dcc) enable bits .......................................... 33 serial port interface (spi) .............................................................. 34 configuration using the spi ..................................................... 34 hardware interface ..................................................................... 34 spi accessible features .............................................................. 35 memory map .................................................................................. 36 reading the memory map register table ............................... 36 memory map register table ..................................................... 37 memory map register description ......................................... 41 applications information .............................................................. 42 design guidelines ...................................................................... 42 spi initialization sequence ....................................................... 42 outline dimensions ....................................................................... 45 ordering guide .......................................................................... 45
data sheet ad9250 rev. e | pag e 3 of 45 r evision h istory 9/2017 rev. d to rev. e changes to channel - specific reg isters section ................................ . 36 changes to table 18 ................................ ................................ ................... 37 changes to figure 63 and table 19 ................................ ........................ 43 5 /2017 rev. c to rev. d change to differential output volta ge (v od ) parameter, table 3 .... 8 deleted synchronization section .................................................. 26 changes to link setup parameters section ................................. 26 deleted clock adjustment register writes section ................... 27 added internal fifo timing optimization section ................. 28 changes to table 14 ........................................................................ 30 changes to channel - sp ecific registers section .......................... 36 deleted transfer register map section ........................................ 37 changes to table 18 ........................................................................ 37 added spi initialization sequence section .................................. 42 added figure 63 and table 19 ; renumbered sequentially ........ 43 deleted jesd204b configuration section ................................... 44 updated outline dime nsions ........................................................ 45 1 / 20 1 6 rev. b to rev. c moved revision history section ..................................................... 3 changes to nyquist clock input options .................................... 22 added synchronization section .................................................... 26 added click adjustment register writes section ...................... 27 changes to link setup parameters section ................................. 27 change to additiona l digital output configuration options section .............................................................................................. 29 added table 14, renumbered sequentially ................................. 30 changes to table 18 ........................................................................ 38 added jesd204b configuration section .................................... 43 1 2 / 20 13 rev. a to rev. b change to features section .............................................................. 1 change to functional block diagram ............................................ 1 chang e to syncin i nput (syncinb+/syncinb?), logic compliance parameter , table 3 ....................................................... 6 changes to data output parameters, table 4 ............................... 8 changes to figure 3 .......................................................................... 9 change to figure 30, added figure 34 through figure 3 7 ; renumbered sequentially .............................................................. 17 changes to table 9 .......................................................................... 20 change to figure 47 ........................................................................ 2 1 c hanges to jesd204b overview section .................................... 2 4 change to configure details options section ............................ 2 6 change to check fchk, checksum of jesd204b interface parameters section .......................................................................... 2 7 changes to figure 54 ...................................................................... 2 8 change s to figure 57 and figure 58 ............................................. 2 9 changes to figure 59 and figure 6 0 ............................................. 30 changes to table 17 ........................................................................ 3 6 updated outline dimensions ........................................................ 4 2 3 / 20 13 rev. 0 to rev. a changes to high level input current and low level input current; table 3 ................................................................................. 6 changes to table 4 ............................................................................ 8 changes to figure 3 caption ........................................................... 9 changes to digital inputs description ; table 8 .......................... 1 1 changes to jesd204b synchronization details section ........... 24 changes to configure detailed options section ........................ 25 changes to fast threshold detection (fda and fdb) section ... 30 deleted built - in self - test (bist) and output test section ...... 3 2 changes to transfer regist er map section .................................. 34 changes to table 17 ........................................................................ 3 5 10/ 20 1 2 revision 0: initial version
ad9250 data sheet rev. e | page 4 of 45 general description the ad9250 is a dual, 14 - bit adc with sampling speeds of up to 250 msps. the ad9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. the adc cores feature a multistage, differential pipelined architecture with integr ated output error correction logic. the adc cores feature wide bandwidth inputs supporting a variety of user - selectable input ranges. an integrated voltage reference eases design considerations. a duty cycle stabilizer is provided to compensate for variati ons in the adc clock duty cycle, allowing the converters to maintain excellent performance. the jesd204b high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. by default, the adc outpu t data is routed directly to the two jesd204 b serial output lane s. these outputs are at cml voltage levels. four modes support any combination of m = 1 or 2 (single or dual converters) and l = 1 or 2 (one or two lanes). for dual adc mode, data can be sent through two lanes at the maximum sampling rate of 250 m sps . h owever, if data is sent through one lane , a sampling rate of up to 1 25 m sps is supported . s ynchronization inputs ( sync inb and s ysref ) are provided . flexible power - down options allow significan t power savings, when desired. programmable overrange level detection is supported for each channel via the dedicated fast detect pins. programming for setup and control are accomplished using a 3 - wire spi - compatible serial interface. the ad9250 is available in a 48 - lead lfcsp and is specified over the industrial temperature range of ?40c to +85c.
data sheet ad9250 rev. e | pag e 5 of 45 specifications adc dc specification s avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ?1.0 dbfs differential input, 1.75 v p - p full - scale input range , duty cycle stabilizer (dcs) enabled, l ink parameters used were m = 2 and l = 2 , unless otherwise noted. table 1 . ad9250 - 170 ad9250 - 250 parameter temperature min typ max min typ max unit resolution full 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full ?16 +16 ?16 +16 mv gain error full ?6 +2 ?6 +2.5 %fsr differential nonlinearity (dnl) full 0.75 0.75 lsb 25c 0.25 0.25 lsb integral nonlinearity (inl) 1 full 2.1 3.5 lsb 25c 1.5 1.5 lsb matching characteristic offset error full ?15 +15 ?15 +15 mv gain error full ?2 +3.5 ?2 +3 %fsr temperature drift offset error full 2 2 ppm/c gain error full 16 44 ppm/c input referred noise vref = 1.0 v 25c 1. 49 1.49 lsb rms analog i nput input span full 1.75 1.75 v p -p input capacitance 2 full 2.5 2.5 pf input resistance 3 full 20 20 k? input common - mode voltage full 0.9 0.9 v power supplies supply voltage avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v dvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v supply current i avdd full 233 260 255 280 ma i drvdd + i dvdd full 104 113 140 160 ma power consumption sine wave input full 607 711 mw standby power 4 full 280 339 mw power - down power full 9 9 mw 1 measured with a low input frequency, full - scale sine wave. 2 input capacitance refers to t he effective capacitance between one differential input pin and its complement. 3 input resistance refers to the effective resistance between one differential input pin and its complement. 4 standby power is measured with a dc input and the clk pin acti ve.
ad9250 data sheet rev. e | page 6 of 45 adc ac specification s avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ? 1.0 dbfs differential input, 1.75 v p - p full - scale input range , link parameters used were m = 2 and l = 2, unless otherwise noted. table 2 . ad9250 - 170 ad9250 - 250 parameter 1 temperature min typ max min typ max unit signal - to - noise - ratio (snr) f in = 30 mhz 25c 72.5 72. 1 dbfs f in = 90 mhz 25c 7 2.0 71. 7 dbfs full 70.7 dbfs f in = 140 mhz 25c 71.4 71.2 dbfs f in = 185 mhz 25c 70.7 70.6 dbfs full 69.3 dbfs f in = 220 mhz 25c 70.1 70.0 dbfs signal - to - noise and distortion (sinad) f in = 30 mhz 25c 71.3 70. 7 dbfs f in = 90 mhz 25c 70. 9 70.5 db fs full 69.6 dbfs f in = 140 mhz 25c 70.3 70.0 dbfs f in = 185 mhz 25c 6 9.6 69.5 dbfs full 68.0 dbfs f in = 220 mhz 25c 6 8 . 9 68. 8 dbfs effective number of bits (enob) f in = 30 mhz 25c 11.5 11.5 bits f in = 90 mhz 25c 11.4 11.4 bits f in = 140 mhz 25c 11.3 11.3 bits f in = 185 mhz 25c 11.1 11.2 bits f in = 220 mhz 25c 10.9 11.0 bits spurious - free dynamic range (sfdr) f in = 30 mhz 25c 9 2 8 9 dbc f in = 90 mhz 25c 9 5 8 6 dbc fu ll 7 8 dbc f in = 140 mhz 25c 9 1 8 6 dbc f in = 185 mhz 25c 8 6 8 8 dbc full 80 dbc f in = 220 mhz 25c 8 5 8 8 dbc worst second or third harmonic f in = 30 mhz 25c ? 9 2 ? 89 dbc f in = 90 mhz 25c ?9 5 ?8 7 dbc full ? 78 dbc f in = 140 mhz 25c ?9 1 ?86 dbc f in = 185 mhz 25c ?8 6 ?8 8 dbc full ? 80 dbc f in = 220 mhz 25c ?8 5 ?88 dbc worst other (harmonic or spur) f in = 30 mhz 25c ?9 5 ?94 dbc f in = 90 mhz 25c ?94 ? 96 dbc full ? 78 dbc f in = 140 mhz 25c ?97 ?96 dbc f in = 185 mhz 25c ?9 6 ? 88 dbc full ? 80 dbc f in = 220 mhz 25c ?9 3 ?9 1 dbc
data sheet ad9250 rev. e | pag e 7 of 45 ad9250 - 170 ad9250 - 250 parameter 1 temperature min typ max min typ max unit two - tone sfdr f in = 184.12 mhz (?7 dbfs), 187.12 mhz (?7 dbfs) 25c 87 84 dbc crosstalk 2 full 95 95 db full power band width 3 25c 1000 1000 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation for a complete set of definitions. 2 crosstalk is measured at 100 mhz with ?1.0 dbfs on one channel and no input on the alternate channel. 3 full power b andwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 db . digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ?1.0 dbfs differential input, 1.75 v p - p full - scale input range , dcs enabled, link paramete rs used were m = 2 and l = 2 , unless otherwise noted. table 3 . parameter temp erature min typ max unit differential clock inputs (clk+, clk?) input clk clock rate full 40 6 25 mhz logic compliance cmos/lvds/lvpecl intern al common - mode bias full 0.9 v differential input voltage full 0.3 3. 6 v p - p input voltage range full a gnd avdd v input common - mode range full 0.9 1.4 v high level input current full 0 +60 a low level input current full ? 60 0 a input capa citance full 4 pf input resistance full 8 10 12 k? rf clock input (rfclk) input clk clock rate full 650 1500 mhz logic compliance cmos/lvds/lvpecl internal bias full 0.9 v input voltage range full agnd avdd v input voltage level high full 1.2 avdd v low full agnd 0.6 v high level input current full 0 +150 a low level input current full ?150 0 a input capacitance full 1 pf input resistance (ac - c oupled) full 8 10 12 k? sync in input ( sync in b +/sync in b ?) logic compliance cmos/ lvds internal common - mode bias full 0.9 v differential input voltage range full 0.3 3.6 v p - p input voltage range full d gnd d vdd v input common - mode range full 0.9 1.4 v high level input current full ?5 +5 a low level input c urrent full ?5 +5 a input capacitance full 1 pf input resistance full 12 16 20 k?
ad9250 data sheet rev. e | page 8 of 45 parameter temp erature min typ max unit sysref input (sysref ) logic compliance lvds internal common - mode bias full 0.9 v differential input voltage range full 0.3 3.6 v p - p input voltage rang e full agnd avdd v input common - mode range full 0.9 1.4 v high level input current full ? 5 +5 a low level input current full ? 5 +5 a input capacitance full 4 pf input resistance full 8 10 12 k? logic input ( rst , cs ) 1 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?5 +5 a low level input current full ?10 0 ?45 a input resistance full 26 k? input capacitance full 2 pf logic in put (sclk/pdwn) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 100 a low level input current full ?10 +10 a input resistance full 26 k? input capacitance full 2 pf logi c inputs (sdio) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 100 a low level input current full ? 10 10 a input resistance full 26 k? inp ut capacitance full 5 pf digital outputs (serdout0/serdout1) logic compliance full cml differential output voltage (v od ) full 400 600 750 mv p -p output offset voltage (v os ) full 0.75 drvdd/2 1.05 v digital outputs (s dio / fda/fdb) high level output voltage (v oh ) full i oh = 50 a full 1.79 v i oh = 0.5 ma full 1.75 v low level output voltage (v ol ) full i ol = 1.6 ma full 0.2 v i ol = 50 a full 0.05 v 1 pull - up. 2 pull - down.
data sheet ad9250 rev. e | pag e 9 of 45 switching specificat ions table 4 . ad9250 - 170 ad9250 - 250 parameter symbol temperature min typ max min typ max unit clock input parameters conversion rate 1 f s full 40 170 40 250 msps sysref setup time to rising edge clk 2 t ref s full 0. 31 0. 31 ns sysref hold time from rising edge clk 2 t ref h full 0 0 ns sysref setup time to rising edge rfclk 2 t refsrf full 0. 50 0. 50 ns sysref hold time from rising edge rfclk 2 t ref h rf full 0 0 ns clk pulse width high t ch divide -by - 1 mode, dcs enabled full 2.61 2.9 3.19 1.8 2.0 2.2 ns divide -by - 1 mode, dcs disabled full 2.76 2.9 3.05 1.9 2.0 2.1 ns divide -by - 2 mode through divide -by - 8 mode full 0.8 0.8 ns aperture delay t a full 1.0 1.0 ns aperture uncertainty (jitter) t j full 0.16 0.16 ps rms data output parameters data output period or unit interval (ui) full l/(20 m f s ) l/(20 m f s ) seconds data output duty cycle 25c 50 50 % data valid time 25c 0.84 0.78 ui pll lock time (t lock ) 25c 25 25 s wake - up time standby 25c 10 10 s adc (power - down) 3 25c 250 250 s output (power - down) 4 25c 50 50 s subclass 0: syncinb falling edge to first valid k.28 characters (delay required for rx cgs start) full 5 5 multiframes subclass 1: sysref rising edge to first valid k.28 characters (delay required for syncb rising edge/rx cgs start) full 6 6 multiframes cgs phase k.28 characters duration full 1 1 multiframe s pipeline delay jesd204b m1, l1 mode (la tency) full 36 36 cycles 5 jesd204b m1, l2 mode (latency) full 59 59 cycles jesd204b m2, l1 mode (latency) full 25 25 cycles jesd204b m2, l2 mode (latency) full 36 36 cycles fast detect (latency) full 7 7 cycles data rate per l ane full 3.4 5.0 5.0 gbps uncorrelated bounded high probability (ubhp) jitter 25c 6 8 ps random jitter at 3.4 gbps full 2.3 ps rms at 5.0 gbps full 1.7 ps rms output rise/fall time full 60 60 ps differential termin ation resistance 25c 100 100 ? out - of - range recovery time full 3 3 cycles 1 conversion rate is the clock rate after the divider. 2 refer to figure 3 for timing diagram. 3 wake - up time adc is defined as the time required for the adc to return to normal operation from power - down mode. 4 wake - up time output is defined as the time required for je sd204b output to return to normal operation from power - down mode. 5 cycles refers to adc conversion rate cycles.
ad9250 data sheet rev. e | page 10 of 45 timing specification s table 5 . parameter test conditions /comments min typ max unit spi timing requirements (s ee figure 62) t ds set up time b etween the data and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s set up time between cs and sclk 2 ns t h hold time between cs an d sclk 2 ns t high minimum period that sclk should be in a logic high state 10 ns t lo w minimum period that sclk should be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figures) 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figures) 10 ns t spi_rst time required after hard or soft reset until spi access is available (not shown in figures) 500 s timing diagrams n ? 36 n ? 35 n ? 34 n ? 33 n ? 1 n + 1 sample n analog input signal clk? clk+ clk? clk+ serdout1 serdout0 sample n ? 36 encoded into 2 8b/10b symbols sample n ? 35 encoded into 2 8b/10b symbols sample n ? 34 encoded into 2 8b/10b symbols 10559-002 figure 2. data output timing 10559-003 t refs t refh t refhrf notes 1. clock input is either rfclk or clk, not both. clk+ clk? sysref+ sysref? rfclk sysref+ sysref? t refsrf figure 3. sysref setup and hold timing
data sheet ad9250 rev. e | pag e 11 of 45 absolute maximum rat ings table 6 . parameter r ating electrical avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0 v d vdd to d gnd ?0.3 v to +2.0 v vin+a/vin+b, vin?a/vin?b to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v rfclk to agnd ?0.3 v to avdd + 0.2 v vcm to agnd ?0.3 v to avdd + 0.2 v cs , pdwn to a gnd ?0.3 v to a vdd + 0.3 v sclk to agnd ?0.3 v to a vdd + 0.3 v sdio to agnd ?0.3 v to a vdd + 0.3 v rst to d gnd ?0.3 v to dvdd + 0.3 v fda, fdb to d gnd ?0.3 v to dvdd + 0.3 v serdout0+, serdout0?, ser dout 1 +, ser dout 1 ? to agnd ?0.3 v to drvdd + 0.3 v syncinb+, syncinb? to dgnd ?0.3 v to dvdd + 0.3 v sys ref +, sysref ? to a gnd ?0.3 v to a vdd + 0.3 v environmental operating temperature range (ambient) ?40c to +85c maximu m junction temperature under bias 150c storage temperature range (ambient) ? 65 c to +125c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal characteris tics the exposed paddle must be soldered to the ground plane for the lfcsp package. this increases the reliability of the solder joints, maximizing the thermal capability of the package. table 7 . thermal resistance package type airf low velocity (m/s ec ) ja 1, 2 jc 1, 3 jb 1, 4 unit 48- lead lfcsp 7 mm 7 mm (cp - 48 - 13 ) 0 2 5 2 1 4 c/w 1.0 2 2 c/w 2. 5 20 c/w 1 per jedec 51 - 7, plus jedec 25 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 p er mil - s td - 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). typical ja is specified for a 4 - layer printed circuit board ( pcb ) with a solid ground plane. as shown in table 7 , airflow increases heat dissipati on, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . esd caution
ad9250 data sheet rev. e | page 12 of 45 pin configuration an d function descripti ons 1 2 3 a vdd dnc pdwn 4 cs 5 sclk 6 sdio 7 dvdd 24 dvdd 23 dgnd 22 serdout0+ 21 serdout0? 20 d r vdd 19 serdout1? 18 serdout1+ 17 dgnd 16 dvdd 15 syncinb? 14 syncinb+ 13 dvdd 44 a vdd 45 vin+b 46 vin?b 47 a vdd 48 a vdd 43 a vdd 42 vcm 41 a vdd 40 a vdd 39 vin+ a 38 vin? a 37 a vdd t op view (not to scale) ad9250 25 dnc 26 dvdd 27 rst 28 dvdd 29 a vdd 30 sysref? 31 sysref+ 32 a vdd 33 clk+ 34 clk? 35 rfclk 36 a vdd 8 dnc 9 dnc 10 fd a 1 1 fdb 12 dvdd notes 1. dnc = do not connec t . do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the ground reference for drvdd and avdd. this exposed paddle must be connected to ground for proper operation. 10559-004 figure 4 . pin configuration (top view) table 8 . pin function desc riptions pin no. mnemonic type description adc power supplies 1, 5, 8, 36, 37, 40, 41, 43, 44, 47, 48 avdd supply analog power supply (1.8 v nominal). 9, 11, 13, 16 , 24, 25, 30 d vdd supply digital power supply (1.8 v nominal). 12, 28, 29, 35 dnc do not connect. 17, 23 dgnd ground reference for dvdd. 20 drvdd supply jesd204b phy serial output driver supply (1.8 v nominal). note that the drvdd power is referenced to the agnd plane. exposed paddle agnd/d r gnd ground the exposed thermal paddle on the bottom of the package provides the ground reference for drvdd and avdd. this exposed paddle must be connected to ground for proper operation. adc analog 2 rfclk in put adc rf clock input. 3 clk ? input adc nyquist clock input complement. 4 clk + input adc nyquist clock input true. 38 vin?a input differential analog input pin (?) for channel a. 39 vin+a input differential analog input pin (+) for channel a. 42 vcm output common - mode level bias output for analog inputs. decouple this pin to ground using a 0.1 f capacitor. 45 vin+b input differential analog input pin (+) for channel b. 46 vin?b input differential analog input pin (?) for channel b. adc fast detect outputs 26 fdb output cha nnel b fast detect indicator (cmos levels). 27 fda output channel a fast detect indicator (cmos levels). digital inputs 6 sysref+ input jesd204b lvds sysref input true . 7 sysref? input jesd204b lvds sysref input complement. 14 syncinb+ input jesd 204b lvds sync input true . 15 syncinb? input jesd204b lvds sync input complement.
data sheet ad9250 rev. e | pag e 13 of 45 pin no. mnemonic type description data outputs 18 serdout1+ output lane b cml output data true. 19 serdout1? output lane b cml output data complement. 21 serdout0? output lane a cml output data compl ement. 22 serdout0+ output lane a cml output data true. dut controls 10 rst input digital reset (active low). 31 sdio input/output spi serial data i/o. 32 sclk input spi serial clock. 33 cs input spi chip select (active low). 34 pdwn input power - down input (active high). the operation of this pin depends on the spi mode and can be configured as power - down or standby (see table 18).
ad9250 data sheet rev. e | page 14 of 45 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, sample rate is maximum for speed grade, dcs enabled, 1.75 v p-p differential input, vin = ?1.0 dbfs, 32k sample, t a = 25c, link parameters used were m = 2 and l = 2, unless otherwise noted. 0 2 04 06 08 0 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 10559-005 f in : 90.1mhz f s : 170msps snr: 71.8dbfs sfdr: 91dbc figure 5. ad9250-170 single-tone fft with f in = 90.1 mhz 0 2 04 06 08 0 amplitude (dbfs) frequency (mhz) 10559-006 f in : 185.1mhz f s : 170msps snr: 71.6dbfs sfdr: 86dbc ?120 ?100 ?80 ?60 ?40 ?20 0 figure 6. ad9250-170 single-tone fft with f in = 185.1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 2 04 06 08 0 amplitude (dbfs) frequency (mhz) 10559-007 f in : 305.1mhz f s : 170msps snr: 69.4dbfs sfdr: 85dbc figure 7. ad9250-170 single-tone fft with f in = 305.1 mhz 0 20 40 60 80 100 120 ?90 ?70 ?50 ?30 ?10 snr snrfs sfdr sfdr dbc sn r /sfdr (dbc and dbfs) input amplitude (dbfs) 10559-008 figure 8. ad9250-170 single-tone snr/sfdr vs. input amplitude (a in ) with f in = 185.1 mhz 60 65 70 75 80 85 90 95 100 0 50 100 150 200 250 300 snr frequency (mhz) snr/sfdr (dbc and dbfs) sfdr 10559-009 figure 9. ad9250-170 single-tone snr/sfdr vs. input frequency (f in ) ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?70 ?50 ?30 ?10 sfdr (dbc) sfdr (dbfs) imd (dbc) imd (dbfs) sfd r /imd (dbc and dbfs) input amplitude (dbfs) 10559-010 figure 10. ad9250-170 two-tone sfdr/imd vs. input amplitude (a in ) with f in1 = 89.12 mhz, f in2 = 92.12 mhz, f s = 170 msps
data sheet ad9250 rev. e | pag e 15 of 45 ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?70 ?50 ?30 ?10 s f dr /i m d ( d b c a n d d b f s ) i n p u t a m p l i t ud e ( d b f s ) sfdr (dbc) sfdr (dbfs) imd (dbc) imd (dbfs) 10559-0 1 1 figure 11 . ad9250 - 170 two - tone sfdr/imd vs. input amplitude (a in ) with f in1 = 184.12 mhz , f in2 = 187.12 mhz, f s = 17 0 msps ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 20 40 60 80 frequenc y (mhz) 10559-012 170 msps 89.12mhz at ?7dbfs 92.12mhz at ?7dbfs sfdr: 91dbc figure 12 . ad9250 - 170 two - tone fft with f in1 = 89.12 mhz , f in2 = 92.12 mhz, f s = 170 msps ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 20 40 60 80 frequenc y (mhz) 10559-013 170 msps 184.12mhz at ?7dbfs 187.12mhz at ?7dbfs sfdr: 86dbc figure 13 . ad9250 - 170 two - tone fft with f in1 = 184.12 mhz , f in2 = 187.12 mhz, f s = 170 msps 70 75 80 85 90 95 100 40 90 140 sfdr_a (dbc) snrfs_a (dbfs) sfdr_b (dbc) snrfs_b (dbfs) snr/sfdr (dbc and dbfs) sample r a te (mhz) 10559-014 figure 14 . ad9250 - 170 single - tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 136 1184 8529 47521 24220 3479 450 0 100,000 200,000 300,000 400,000 500,000 600,000 n ? 6 n ? 4 n ? 2 n n + 2 n + 4 n + 6 number of hits output code 2,096,064 total hits 1.4925 lsb rms 555924 498226 387659 281445 109722 177569 10559-015 figure 15 . ad9250 - 170 grounded input histogram ?120 ?100 amplitude (dbfs) ?80 ?60 ?40 ?20 0 0 50 100 125 frequenc y (mhz) 10559-016 f in : 90.1mhz f s : 250msps snr: 71.8dbfs sfdr: 85dbc figure 16 . ad9250 - 250 single - tone fft with f in = 90.1 mhz
ad9250 data sheet rev. e | page 16 of 45 amplitude (dbfs) 0 50 100 ?120 ?100 ?80 ?60 ?40 ?20 0 frequenc y (mhz) 10559-017 f in : 185.1mhz f s : 250msps snr: 70.7dbfs sfdr: 85dbc figure 17 . ad9250 - 250 single - tone fft with f in = 185.1 mhz amplitude (dbfs) 0 50 100 ?120 ?100 ?80 ?60 ?40 ?20 0 frequenc y (mhz) 10559-018 f in : 305.1mhz f s : 250msps snr: 69.1dbfs sfdr: 82dbc figure 18 . ad9250 - 250 single - tone fft with f in = 305.1 mhz 0 20 40 60 80 100 120 ?100 ?80 ?60 ?40 ?20 0 snr (dbc) snr/sfdr (dbc and dbfs) sfdr (dbc) snr (dbfs) sfdr (dbfs) ain (dbfs) 10559-019 figure 19 . ad9250 - 250 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 185.1 mhz 60 70 80 90 100 0 100 200 300 snr (dbc) sfdr (dbfs) frequenc y (mhz) snr/sfdr (dbc and dbfs) 10559-020 figure 20 . ad9250 - 250 single - tone snr/sfdr vs. input frequency (f in ) ?120 ?100 ?80 ?60 ?40 ?20 0 ?100 ?80 ?60 ?40 ?20 0 sfdr (dbfs) sfdr (dbc) imd (dbc) ain (dbfs) sfdr/imd (dbc and dbfs) imd (dbfs) 10559-021 figure 21 . ad9250 - 250 two - tone sfdr/imd vs. input amplitude (a in ) with f in1 = 89.12 mhz , f in2 = 92.12 mhz, f s = 250 msps sfdr/imd (dbc and dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 ?100 ?80 ?60 ?40 ?20 0 sfdr (dbc) imd (dbc) imd (dbfs) sfdr (dbfs) input amplitude (dbfs) 10559-022 figure 22 . ad9250 - 250 two - tone sfdr/imd vs. input amplitude (a in ) with f in1 = 184.12 mhz , f in2 = 187.12 mhz, f s = 250 msps
data sheet ad9250 rev. e | pag e 17 of 45 amplitude (dbfs) 0 50 frequenc y (mhz) 100 ?120 ?100 ?80 ?60 ?40 ?20 0 10559-023 250msps 89.12mhz at ?7dbfs 92.12mhz at ?7dbfs sfdr: 86.4dbc figure 23 . ad9250 - 250 two - tone fft with f in1 = 89.12 mhz , f in2 = 92.12 mhz, f s = 250 msps amplitude (dbfs) frequenc y (mhz) 0 50 100 ?120 ?100 ?80 ?60 ?40 ?20 0 10559-024 250msps 184.12mhz at ?7dbfs 187.12mhz at ?7dbfs sfdr: 84dbc figure 24 . ad9250 - 250 two - tone fft with f in1 = 184.12 mhz , f in2 = 187.12 mhz, f s = 250 msps snr/sfdr (dbc and dbfs) 70 75 80 85 90 95 100 40 50 100 150 200 250 sample rate (msps) sfdr_a (dbc) sfdr_b (dbc) snr_a (dbc) snr_b (dbc) 10559-025 figure 25 . ad9250 - 250 single - tone snr/sfdr vs. sample rate (f s ) with f in = 9 0.1 mhz 418 2142 10549 52008 26647 4856 913 0 100k 200k 300k 400k 500k 600k n ? 6 n ? 4 n ? 2 n n + 2 n + 4 n + 6 number of hits output code 2,095,578 total hits 1.4535 lsb rms 570587 380706 276088 163389 109133 498242 10559-026 figure 26 . ad9250 - 250 grounded input histogram
ad9250 data sheet rev. e | page 18 of 45 equivalent circuits v i n a v d d 10559-027 figure 27 . equivalent analog input circuit 0 . 9 v 15k ? 15k ? c l k + c l k ? a v d d a v d d a v d d 10559-028 figure 28 . equivalent clock lnput circuit bias control 10k ? rfclk interna l clock driver 0.5pf 10559-029 a v d d figure 29 . equivalent rf clock lnput circuit v c m drv d d serdoutx+ serdoutx? 3m a 3m a 3m a 3m a r t e r m 10559-030 drv d d drv d d figure 30 . digital cml output circuit 400 ? sdio 31k ? av d d 10559-226 figure 31 . equivalent sdio circuit 400 ? 31k ? av d d sclk/pwdn 10559-225 figure 32 . equivalent sclk or pdwn input circuit 10559-224 400 ? 28k ? avdd av d d cs figure 33 . equivalent cs input circuit 0 . 9 v 1 7 k ? 1 7 k ? sysref+ sysref? a v d d a v d d a v d d 10559-134 figure 34 . equivalent sysref input circuit
data sheet ad9250 rev. e | page 19 of 45 rst 400 ? 28k ? dvdd dvdd 10559-333 figure 35. equivalent rst input circuit 400 vcm ? avdd 10559-136 figure 36. equiva lent vcm circuit 0.9v 17k? 17k? syncinb+ syncinb? dvdd dvdd dvdd 10559-122 figure 37. syncinb circuit
ad9250 data sheet rev. e | page 20 of 45 theory of operation the ad9250 has two analog input channels a nd two jesd204b output lane s. the signal passes through several stages before appearing at the output port(s). the dual adc design can be used for diversity reception of signals , where the adcs operate identically on the same carrier b ut from two separate antennae. the adcs can also be operated with independent analog input s. the user can sample frequencies from dc to 300 mhz using appropriate low - pass or band - pass filtering at t he adc inputs with little los s in adc performance. operation to 400 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. a s ynchronizat i on capability is provided to allow synchronized timing between multiple device s. programm ing and control of the ad9250 are accomplished using a 3 - pin , spi - compatible serial interface. adc architecture the ad9250 a rchitecture consists of a dual , front - end , sample - and - hold c ircuit, followed by a pipelined switched capacitor adc. the quantized outputs from each stage are combined into a final 14 - bit result in the digital correction logic. the pipelined architecture pe rmits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution fl ash adc con nected to a switched capacitor digital - to - analog converter (dac) and an interstage residue amplifier (mdac). the mdac magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundanc y is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differential sampling circuit that can be ac - or dc - coupled in differential or single - ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. analog input conside rat ions the analog input to the ad9250 is a differential , switched capacitor circuit that has been designed for optimum performance while processing a differential input signal. the clock signal alt ernatively switches the input between sample mode and hold mode (see the configuration shown in figure 38 ). when the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging cu rrents. this passive network creates a low - pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, reduce the shunt capacitors. in combination with the drivin g source impedance, the shunt capacitors limit the input bandwidth. refer to the an - 742 application note , frequency domain response of switched - capacitor adcs ; the an - 827 application note , a resonant approach to interfacing amplifiers to switched - capacitor adcs ; and the analog dialogue article, tran sformer - coupled front - end for wideband a/d converters , for more information on this subject. c p ar 1 c p ar 1 c p ar 2 c p ar 2 s s s s s s c f b c f b c s c s b i a s b i a s v i n + h v i n ? 10559-034 figure 38 . switched - capacitor input for best dynamic performance, match the source impedances driving vin+ and vin? and differentially balance the inputs. input common mode the analog inputs of t he ad9250 are not internally dc biased. in ac - coupled applications, the u ser must provide this bias externally. setting the device so that v cm = 0.5 avdd (or 0.9 v) is recommended for optimum performance . an on - board common - mode voltage reference is included in the design and is available from t he vcm pin. using the vcm outpu t to set the input common mode is recommended. optimum perform ance is achieved when the common - mode voltage of th e analog input is set by the vcm pin voltage (typically 0.5 avdd). decouple t he vcm pin to ground by using a 0.1 f capacitor, as described i n the applications information section. place t his decoupling capacitor close to the pin to minimize the series resistance and inductance between the part and this capacitor. differential input configurations optimum performance i s achieved while driving the ad9250 in a differential input configuration. for baseband applications, the ad8138 , ada4937 - 2 , ada4938 - 2 , and ada4930 - 2 differ - ential driver s provide excellent performance a nd a flexible interface to the adc .
data sheet ad9250 rev. e | page 21 of 45 the output common-mode voltage of the ada4930-2 is easily set with the vcm pin of the ad9250 (see figure 39), and the driver can be configured in a sallen-key filter topology to provide band-limiting of the input signal. vin 76.8 ? 120 ? 0.1f 200 ? 200 ? 90? 0.1f avdd 33? 33? 33? 15? 15? 5pf 15pf 15pf adc vin? vin+ vcm ada4930-2 10559-035 figure 39. differential input configuration using the ada4930-2 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 40. to bias the analog input, the vcm voltage can be connected to the center tap of the secondary winding of the transformer. 2v p-p 49.9 ? 0.1f r1 r1 c1 adc vin+ vin? vcm c2 r2 r3 r2 c2 r3 0.1f 33? 10559-036 figure 40. differential transformer-coupled configuration consider the signal characteristics when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz. excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the ad9250 . for applications where snr is a key parameter, differential double balun coupling is the recommended input configuration (see figure 41). in this configuration, the input is ac-coupled and the vcm voltage is provided to each input through a 33 resistor. these resistors compensate for losses in the input baluns to provide a 50 impedance to the driver. adc r1 0.1f 0.1f 2v p-p vin+ vin? vcm c1 c2 r1 r2 r2 0.1f s 0.1f c2 33 ? 33 ? s p a p r3 r3 0.1f 33 ? 10559-037 figure 41. differential double balun input configuration in the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. based on these parameters, the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. table 9 displays recommended values to set the rc network for different input frequency ranges. however, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. note that the values given in table 9 are for each r1, r2, c1, c2, and r3 components shown in figure 40 and figure 41. table 9. example rc network frequency range (mhz) r1 series () c1 differential (pf) r2 series () c2 shunt (pf) r3 shunt () 0 to 100 33 8.2 0 15 24.9 100 to 400 15 8.2 0 8.2 24.9 >400 15 3.9 0 3.9 24.9 an alternative to using a transformer-coupled input at frequencies in the second nyquist zone is to use an amplifier with variable gain. the ad8375 or ad8376 digital variable gain amplifier (dvgas) provides good performance for driving the ad9250. figure 42 shows an example of the ad8376 driving the ad9250 through a band-pass antialiasing filter. ad8376 adc 1h 1h 1nf 1nf vpos vcm 15pf 68nh 20k ?U 2.5pf 301 ? 165 ? 165 ? 5.1pf 3.9pf 180nh 1000pf 1000pf notes 1. all inductors are coilcraft ? 0603cs components with the exception of the 1h choke inductors (coilcraft 0603ls). 2. filter values shown are for a 20mhz bandwidth filter centered at 140mhz. 180nh 220nh 220nh 10559-038 figure 42. differential input configuration using the ad8376 voltage reference a stable and accurate voltage reference is built into the ad9250 . the full-scale input range can be adjusted by varying the reference voltage via the spi. the input span of the adc tracks the reference voltage changes linearly. clock input considerations the ad9250 has two options for deriving the input sampling clock, a differential nyquist sampling clock input or an rf clock input (which is internally divided by 4). the clock input is selected in register 0x09 and by default is configured for the nyquist clock input. for optimum performance, clock the ad9250 nyquist sample clock input, clk+ and clk?, with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or via capacitors. these pins are biased internally (see figure 43) and require no external bias. if the clock inputs are floated, clk? is pulled slightly lower than clk+ to prevent spurious clocking.
ad9250 data sheet rev. e | page 22 of 45 nyquist clock input options the ad9250 nyquist c lock input supports a differential clock between 40 mhz to 62 5 mhz. the clock input structure supports differential input voltages from 0.3 v to 3.6 v and is therefore compatible with various logic family inputs , such as cmos, lvds , and lvpecl. a sine wave input is also accepted, but higher slew rates typically prov ide optimal performance. clock source jitter is a critical parameter that can affect performance, as described in the jitter considerations section. if the inputs are floated, pull the clk? pin low to prevent spurious clocking. the nyquist c lock input pin s, clk+ and clk ?, are internally biased to 0.9 v and have a typical input impedance of 4 pf in parallel with 10 k ? ( see figure 43) . the input clock is typic ally ac - coupled to clk+ and clk ? . some typical clock drive circuits are presented in figure 44 through figure 47 for reference. a v d d c l k + 4 p f 4 p f c l k ? 0 . 9 v 10559-039 figure 43 . equivalent nyquist clock input circuit for application s where a single - ended low jitter clock between 40 mhz to 200 mhz is available, an rf t ransformer is recom - mended. an example using an rf transformer in the clock network is shown in figure 44 . at frequencies above 200 mhz, an rf balun is recommended, as seen in figure 45 . the back - to - back schottky diodes across the transformer secondary limit clock excursions into the ad9250 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding throug h to other portions of the ad9250 , yet preserves the fast ri se and fall times of the clock, which are critical to low jitter performance. 390 p f 390 p f 390 p f s ch o tt k y d io d es: h sms 282 2 c l o c k i n p u t 50 ? 100 ? c l k ? c l k + ad c m i n i - c i rc u i ts ? ad t 1 - 1 wt , 1 : 1 z x f mr 10559-040 figure 44 . transformer - coupled differential clock (up to 200 mhz) 390 p f 390 p f 390 p f c l o c k i n p u t 1 n f 25 ? 25 ? c l k ? c l k + s ch o tt k y d io d es: h sms 282 2 ad c 10559-041 figure 45 . balun - coupled differential clock (up to 6 25 mh z) in some cases , it is desirable to buffer or generate multiple clock s from a single source. in those cases , analog devices , inc., offers clock drivers with excellent jitter performance. figure 46 shows a typical pecl d river circ uit that u s e s pecl drivers such as the ad9510 , ad9511 , ad9512 , ad9513 , ad9514 , ad9515 , ad95 16- 0 through ad9516 - 5 device family, ad9517 - 0 through ad9517 - 4 device family, ad9518 - 0 through ad9518 - 4 device family, ad9520 - 0 through ad9520 - 5 device family, ad9522 - 0 through ad9522 - 5 device family, ad9523 , ad9524 , and adclk905 / adclk907 / adclk925 100 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 240 ? 240 ? pe c l dr i ver 50k ? 50k ? c l k ? c l k + c l o c k i n p u t c l o c k i n p u t ad 95x x ad c 10559-042 figure 46 . different ial pecl sample clock (up to 6 25 mhz) analog devices also offers lvds clock drivers with excellent jitter performance. a typical circuit is shown in figure 47 and uses lvds drivers such as the ad9510 , ad9511 , ad9512 , ad9513 , ad9514 , ad9515 , ad9516 - 0 through ad9516 - 5 device family, ad9517 - 0 throu gh ad9517 - 4 device family, ad9518 - 0 through ad9518 - 4 device family, ad9520 - 0 through ad9520 - 5 device family, ad9522 - 0 through ad9522 - 5 device family, ad9523 , and ad9524 . 1 0 0 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 50k ? 50k ? c l k ? c l k + c l o c k i n p u t c l o c k i n p u t ad 95x x l v d s dr i ver ad c 10559-043 figure 47 . differential lvds sample clock (up to 625 mhz) rf clock input options the ad9250 rf c lock input support s a single - ended clock between 625 ghz to 1.5 ghz. the equivalent rf c lock input circuit is shown in figure 48 . the input is self bias ed to 0.9 v and is typically ac - coupled. the input has a typical input impedance of 10 k ? in parallel with 1 pf at the rfclk pin. bias control 10k ? rfclk interna l clock driver 1pf 10559-044 figure 48 . equivalent rf clock input circuit it is recommended to drive the rf clock input of the ad9250 wit h a pecl or sine wave signal with a minimum signal amplitude of 600 mv peak to peak. regardless of the type of signal being use d, clock source jitter is of the most concern, as described in the jitter considerations section. figure 49 shows the preferred method of clocking when using the rf clock input on the ad9250 . it is recommended to u s e a 50 ? tran smission line to route the clock signal to the rf clock input of the ad9250 due to the high frequency nature of the signal and terminate the transmission line close to the rf clock in put. rfclk ad c 50 ? tx line rf clock input 0.1 f 50 ? 10559-045 figure 49 . typical rf clock input circuit
data sheet ad9250 rev. e | page 23 of 45 0.1f 0.1f 0.1f 0.1f lvpecl driver ad9515 127? v dd 82.5 ? 127? 82.5 ? c lock input c lock input rfclk adc 50 ? tx line 0.1f 50 ? 10559-046 figure 50. differential pecl rf clock input circuit figure 50 shows the rf clock input of the ad9250 being driven from the lvpecl outputs of the ad9515 . the differential lvpecl output signal from the ad9515 is converted to a single- ended signal using an rf balun or rf transformer. the rf balun configuration is recommended for clock frequencies associated with the rf clock input. input clock divider the ad9250 contains an input clock divider with the ability to divide the nyquist input clock by integer values between 1 and 8. the rf clock input uses an on-chip predivider to divide the clock input by four before it reaches the 1 to 8 divider. this allows higher input frequencies to be achieved on the rf clock input. the divide ratios can be selected using register 0x09 and register 0x0b. register 0x09 is used to set the rf clock input, and register 0x0b can be used to set the divide ratio of the 1-to-8 divider for both the rf clock input and the nyquist clock input. for divide ratios other than 1, the duty-cycle stabilizer is automatically enabled. rfclk nyquist clock 1 to 8 divider 10559-047 4 figure 51. ad9250 clock divider circuit the ad9250 clock divider can be synchronized using the external sysref input. bit 1 and bit 2 of register 0x3a allow the clock divider to be resynchronized on every sysref signal or only on the first signal after the register is written. a valid sysref causes the clock divider to reset to its initial state. this synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9250 contains a dcs that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the ad9250. jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. the duty cycle control loop does not function for clock rates less than 40 mhz nominally. the loop has a time constant associated with it that must be considered when the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time that the loop is not locked, the dcs loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter (t j ) can be calculated by snr hf = ?10 log[(2 f in t jrms ) 2 + 10 )10/( lf snr ? ] in the equation, the rms aperture jitter represents the root-mean- square of all jitter sources, which include the clock input, the analog input signal, and the adc aperture jitter specification. if undersampling applications are particularly sensitive to jitter, as shown in figure 52. 80 75 70 65 60 55 50 1 10 100 1000 input frequency (mhz) snr (dbc) 0.05ps 0.2ps 0.5ps 1ps 1.5ps measured 10559-048 figure 52. ad9250 -250 snr vs. input frequency and jitter
ad9250 data sheet rev. e | page 24 of 45 treat t he clock input as an analog signal in cases where aperture jitter may affect the dyna mic range of the ad9250 . separate the p ower supplies for the clock drivers from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controll ed oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or an other meth od ), retim e it by the original clock at the last step. refer to t he an - 501 application note , aperture uncertainty and adc system performance and the an - 756 application note , sampled systems and the effects of clock phase noise and jitte r for more informatio n about jitter performance as it relates to adcs. power dissipation an d standby mode as shown in figure 53 , the power dissipated by the ad9250 is proportional to its sa mple rate. the data in figure 53 w as taken using the same operating conditions as those used for the typical performance characteristics section . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 40 90 140 190 240 total power (w) power (avdd) power (dvdd) total power encode frequency (msps) 10559-149 figure 53 . ad9250 - 250 power vs. encode rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the ad9250 is placed in power - d own mo de . in this state, the adc typically dissipates about 9 mw. asserting the pdwn pin low returns the ad9250 t o its normal operati ng mode. low power dissipation in power - down mode is achieved by shu tting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power - down mode and then must be recharged when returning to nor mal operation. as a result, wake - up time is related to the time spent in power - down mode , and shorter power - down cycles result in proportion ally short er wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see th e memory map register description section and the an - 877 application note , interfacing to high speed ad cs via spi , for additional details.
data sheet ad9250 rev. e | pag e 25 of 45 digital outputs jesd204b transmit top level d escription the ad9250 digital output uses the jedec standard no. jesd204b, serial interface for data converters . jesd204b is a protocol to link the ad9250 to a digital processing device over a serial interface of up to 5 gbps link speeds (3.5 gbps , 14- b it adc data rate). the benefits of the jesd204b interfa ce include a reduction in required board area for data interface routing and the enabl ing of smaller packages for converter and logic devices. the ad9250 supports single or dual lane interfaces. j esd204b overview the jesd204b data transmit block assembles the parallel data from the adc into frames and uses 8 b /10 b encoding as well as optional scrambling to form serial output data. lane synchronization is supported using special characters during the initial establishment of the link , and additional synchronization is embedded in the data stream thereafter. a matching external receiver is required to lock onto the serial data stream and recover the data and clock . for additional details on the jesd204 b interface, refer to the jesd204b standard. the ad9250 jesd204b transmit block maps the output of the two adc s over a link. a link can be configured to use either single or dual serial differenti al outputs that are called lanes. the jesd204b specification refers to a number of parameters to define the link , and these parameters must match between the jesd204b transmitter ( ad9250 output) a nd receiver. the jesd204b l ink is described according to the following parameters: ? s = samples transmitted/single converter/frame cycle ( ad9250 value = 1) ? m = number of converters/converter devic e ( ad9250 value = 2 by default, or can be set to 1 ) ? l = number of lanes/converter device ( ad9250 value = 1 or 2) ? n = converter resolut ion ( ad9250 value = 14) ? n = total number of bits per sample ( ad9250 value = 16) ? cf = number of control words/frame clock cycle/converte r device ( ad9250 value = 0) ? cs = number of control bits/conversion sample (configurable on the ad9250 up to 2 bits) ? k = number of frames per multiframe (configurable on the ad9250 ) ? hd = high density mode ( ad9250 value = 0) ? f = octets/frame ( ad9250 value = 2 or 4, dependent upon l = 2 or 1) ? c = control bit (overrange, overflow, underflow ; a vailable on the ad9250 ) ? t = tail bit (available on the ad9250 ) ? scr = scrambler enable/disable (configurable on the ad9250 ) ? fchk = checksum for the jesd204b parameters (automatically calculated and stored in register map) figure 54 shows a simplified block diagram of the ad9250 jesd204b link. by default, the ad92 50 is configured to use two converters and two lanes. converter a data is output to ser dout 0 +/ ser dout 0 ?, and c onverter b is output to ser dout 1 +/ ser dout 1 ? . the ad9250 allows for other configurations such as combining the outputs of both converters onto a single lane or changing the mapping of the a and b digital output paths. these modes are setup through a quick configuration register in the spi register map , along with additional customizable options. by default in the ad9250 , the 14 - bit converter word from each converter is broken into two octets (8 bits of data). bit 13 ( msb ) through bit 6 are in the first octet. the second octet contains bit 5 through bit 0 ( lsb ) , and two tail bits are added to fill the second octet . the tail bits can be configured as zeros, pseudo - random number sequence or control bits indicating overrange, underrange , or v alid data conditions. the two resulting octets can be scrambled. scrambling is optional ; however, it is available to avoid spectral peaks when trans mitting similar digital data patterns. the scrambler uses a self synchronizing , polynomial - based algorithm defined by the equation 1 + x 14 + x 15 . the descrambler in the receiver should be a self - synchronizing version of the scrambler polynomial. the two o ctets are then encoded with an 8 b /10 b encoder. the 8b/10b encoder works by taking eight bits of data (an octet) and encoding them into a 10 - bit symbol. figure 55 shows how the 14- bit data is taken from the adc, the tail bits are a dded, the two octets are scrambled, and how the octets are encoded into two 10- bit symbols. figure 55 illustrates the default data format. at the data link layer, in addition to the 8b/10b encoding, the character replacement is used to allow the receiver to monitor frame alignment. the c haracter replacement process occurs on the frame and multiframe boundaries , and implementation depends on which boundary is occurring , and if scrambling is enabled. if scrambling is disabled, the foll owing applies. if the last scrambled octet of the last frame of the multi frame equals the last octet of the previous frame, the transmitter replaces the last octet with the control character /a/ = /k28.3/. on other frames within the multiframe, if the last octet in the frame equals the last octet of the previous frame, the transmitter replaces the last oct et with the control character /f /= /k28.7/. if scrambling is enabled, the following applies. if the last octet of the last frame of the multiframe equals 0x7c, the transmitter replaces the last octet with the control character /a/ = /k28.3/. on other frames within the multiframe, if the last octet equals 0xfc, the transmitter replaces the last oct et with the control character /f / = /k28.7/. refer to jedec s tandard no. 204b - july 2011 for additional information about the jesd204b interface. section 5.1 covers the transport layer and data format details and section 5.2 covers scrambling and descrambling .
ad9250 data sheet rev. e | page 26 of 45 jesd204b synchronization deta ils the ad9250 supports jesd204b subclass 0 and subclass 1 and establishes synchronization of the link through one or two control signals, sy nc and subclass 1 also use sy sref , and a common device clock. sysref and sync are c ommon to all converter devices for alignment purposes at the system level. the synchronization process is accomplished over three phases: code group synchronization (cgs), initial lane alignment sequenc e (ilas) , and data transmission . i f scrambling is enab led, scrambling begins with the first data byte following the last alignment character of the ilas. cgs and ilas phases are not scrambled . cgs phase in th e cgs phase, the jesd204b transmit block transmits /k28.5/ characters. the receiver (external logic device) must locate k28.5 characters in its input data stream using clock and data recover y (cdr) techniques. wh e n in subclass 1 mode, the receiver locks onto the k28.5 characters . once de tected, the receiver initiate s a sysref edge so that the ad9250 transmit data establishes a local multifra me clock (lmfc) internally. the sysref edge also resets any sampling edges within the adc to align sampling instances to the lmfc. this is important to main tain synchronization across multiple devices. if subclass 0: at the next receivers internal clock; if subclass 1: at the next receivers lmfc boundary, t he receiver or logic device de - assert s the sync~ signal (syncinb goes high ) , and the transmitter blo ck begin s the ilas phase. ilas phase in th e ilas phase, the transmitter send s out a known pattern , and the receiver align s all lanes of the link and verif ies the parameters of the link. the ilas phase begins after sync~ has been de - asserted (goes high). if subclass 0: the transmitter begins ilas at the next transmitters internal clock; if subclass 1: at the next transmitters internal lmfc boundary, t he transmit block begin s to transmit four multiframes. dummy samples are inserted between the required c haracters so that full multiframes are transmitted. the four multiframes include the following: ? multi f rame 1: begins with a n /r/ character [k28.0] and ends with an /a/ character [k28.3]. ? multi f rame 2: begins with an /r/ character followed by a /q/ [k28.4] character, followed by link configuration parameters over 14 configuration octets (see table 10) , and ends with an /a/ character. many of the parameters values are of the notation o f the value ? 1. ? multi f rame 3: i s the same as m ulti frame 1 . ? multi f rame 4: i s the same as multi frame 1 . data transmission phase in th e data transmission phase, frame alignment is monitored with control characters. character replacement is used at the end of frames. character replacement in the transmitt er occurs in the following instances: ? if scrambling is disabled and the last octet of the frame or multiframe equals the octet value of the previous frame. ? i f scrambling is enabled and the last octet of the multiframe is equal to 0x7c , or the last octet of a frame is equal to 0xfc. table 10. fourteen configuration o ctets of the ilas phase no. bit 7 ( msb ) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ( lsb ) 0 did [ 7:0 ] 1 bid [ 3:0 ] 2 lid [ 4:0 ] 3 scr l[4:0] 4 f [ 7:0 ] 5 k [ 4:0 ] 6 m [ 7:0 ] 7 cs [ 1:0 ] n [ 4:0 ] 8 subclass [ 2:0 ] n[ 4:0 ] 9 jesdv [ 2:0 ] s[ 4:0 ] 10 hd cf [ 4:0 ] 11 r eserved , d ont c are 12 reserved, dont care 13 fchk [ 7:0 ] link setup parameters the following demonstrate s how to configure the ad9250 jesd204b interf ace paremeters . these details are a subset of the spi initialization sequence shown in figure 63 and table 19. t he steps to configure the output include the following: 1. d isable lanes before changing the configuration . 2. s elect the quick configuration option . 3. configure the detailed options . 4. check fchk, checksum of jesd204b interface parameters . 5. s et the additional digital outpu t configuration options . 6. r e - enable lane(s) . disable l anes before changing configuration before modifying the jesd204b link parameters, disable the link and h o ld it in reset. this is accomplished by writing l ogic 1 to register 0x5f , bit 0 . select quick conf iguration option write to register 0x5e, the 204b quick configuration register to select the configuration options. see table 13 for configuration options and resulting jesd204b parameter values. ? 0x11 = o ne conver ter, one lane ? 0x12 = o ne converter, two lanes ? 0x21 = t wo converters, one lane ? 0x22 = t wo converters, two lanes
data sheet ad9250 rev. e | pag e 27 of 45 configure detailed options configure the t ail b its and c ontrol bits . ? with n = 16 and n = 14, there are two bits available per sample for trans mitting additional information over the jesd204b link. the options are tail bits or control bits. by default, tail bits of 0b00 value are used. ? tail bits are dummy bits sent over the link to complete the two octets and do not convey any information about t he input signal. tail bits can be fixed zeros (default) or psuedo random numbers (reg ister 0x5f , bit 6 ). ? one or two control bits can be used instead of the tail bits through r egister 0x72 , bits[ 7:6 ] . the tail bits can be set using reg ister 0x14 , bits[ 7:5 ] , and can be enabled using address 0x5f, bit 6 . set lane identification values . ? jesd204b allows parameters to identify the d evice and l ane. these parameters are transmitted during the ilas phase , and they are accessible in the internal registers. ? there ar e three identification values : d evice identification (did ), b ank identification (bid ) , and l ane identification (lid ). did and bid are device specific ; therefore , they can be used for link identification. set n umber of frames per m ultiframe, k ? per the jesd2 04b specification, a multiframe is defined as a group of k successive frames, where k is between 1 and 32, and it requires that the number of octets be between 17 and 1024. the k value is set to 32 by default in reg ister 0x70 , bits [ 7 :0 ] . note that register 0x70 represents a value of k ? 1 . ? the k value can be changed ; however, it must comply with a few conditions. the ad9250 uses a fixed value for octets per frame [f] based on the jesd204b quick co nfiguration setting. k must also be a multiple of 4 and conform to the following equation. 32 k c eil (17/ f ) ? the jesd204b specification also calls for the number of octets per multiframe (k f) to be between 17 and 1024. the f value is fixed through t he quick configuration setting to ensure this relationship is true. table 11. jesd204b configurable identification values did value register , bits value r ange lid ( lane 0 ) 0x6 6 , [ 4:0 ] 0 31 lid ( lane 1 ) 0x6 7 , [ 4:0 ] 0 31 did 0x64 , [ 7:0 ] 0 255 bid 0x65 , [ 3:0 ] 0 15 scramble, scr . ? scrambling can be enabled or disabled by setting r egister 0x6e , bit 7. by default, scrambling is enabled. per the jesd204b protocol, scrambling is only functional after the l ane synchronization has complete d. select l ane synchronization o ptions . most of the synchronization features of the jesd204b interface are enabled by default for typical applications. in some cases, these features can be disabled or modified as follows : ? ilas enabling is controlled in re g ister 0x5f , bits [ 3:2 ] and by default is enabled. optionally, to support some unique instances of the interfaces (such as nmcda - sl), the jesd204b interface can be programmed to either disable the ilas sequence or continually repeat the ilas sequence . the ad9250 has fixed values of some of the jesd204b interface parameters , and they are as follows: ? [n] = 14: number of bits per converter is 14, in r egister 0x72 , bits [ 4:0 ] ; register 0x72 represents a value of n ? 1 . ? [n] = 16: number of bits per sample is 16, in r egister 0x73 , bits [ 4:0 ] ; register 0x73 represents a value of n ? 1 . ? [cf] = 0: number of control words/ frame clock cycle/converter is 0, in r egister 0x75 , bits [ 4:0 ] . ve rif y r ead only values: l anes pe r link (l) , octets per frame (f) , number of converters (m), and samples per converter per frame ( s ). the ad9250 calculates values for some jesd204b parameters based on other setting s , particularly the quick configuration register selection. the read only values here are available in the register map for verification. ? [l] = l anes per link can be 1 or 2, read the values from r egister 0x6e , bit 0 ? [f] = o ctets per frame can be 1, 2 , or 4, read the val ue from r egister 0x6f , bits [ 7 :0 ] ? [hd] = h igh d ensity mode can be 0 or 1, read the value from r egister 0x75 , bit 7 ? [m] = n umber of converters per link can be 1 or 2, read the value from register 0x71 , bit s[ 7: 0 ] ? [s] = s amples per converter per frame can b e 1 or 2, read the value from register 0x74 , bit s[ 4: 0 ] check fchk, checksum of jesd204b interface parameters the jesd204b parameters can be verified through the checksum value [fchk] of the jesd204b interface parameters. each lane has a fchk value associat ed with it. the fchk value is transmitted during the ilas secon d m ultiframe and can be read from the internal registers. the c hecksum value is the modulo 256 sum of the parameters listed in the no. column of table 12. the c hecksum is calculated by adding the parameter fields before they are packed into the octets shown in table 12. the fchk for the lane configuration for data coming out of lane 0 can be read from register 0x7 8 . similarly, the f chk for the lane configuration for data coming out of lane 1 can be read from r egister 0x7 9 .
ad9250 data sheet rev. e | page 28 of 45 table 12. jesd204b configuratio n table used in ilas and chksum calculation no. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 0 did[7:0] 1 bid[3:0] 2 lid[4:0] 3 scr l[4:0] 4 f[7:0] 5 k[4:0] 6 m[7:0] 7 cs[1:0] n[4:0] 8 subclass[2:0] n[4:0] 9 jesdv[2:0] s[4:0] 10 cf[4:0] additional digital output configuration options other data format controls include the following: ? invert polarity of serial output data: register 0x60, bit 1. ? adc data format (offset binary or twos complement): register 0x14, bits[1:0]. ? options for interpreting single on sysref and syncinb: register 0x3a. see table 14 for additional descriptions of register 0x3a controls. ? option to remap converter and lane assignments, register 0x82 and register 0x83. see figure 54 for simplified block diagram. re-enable lanes after configuration after modifying the jesd204b link parameters, enable the link so that the synchronization process can begin. this is accomplished by writing logic 0 to register 0x5f, bit 0. internal fifo timing optimization each lane of the of the ad9250 jesd204b digital path includes an internal fifo situated between the framer and serializer, which operate from two different clock domains, the adc sample clock and jesd204b pll domains. to optimize the write and read pointers against possible fifo overflow (or underflow) under extreme temperature changes and inconsistent power-up conditions, additional steps are required to increase the timing margin. the procedures described in step 15 of table 19 adjust the write clock phase (via register 0xee and register 0xef) with respect to the read clock to optimize the timing margin. converter a converter b converter b input converter a input sysref syncinb converter b sample converter a sample ad9250 dual adc lane 0 lane 1 serdout0 serdout1 lane 1 lane 0 a a b b primary converter input [0] primary lane output [0] primary converter input [0] primary lane output [0] jesd204b lane control (m = 1, 2; l = 1, 2) lane mux (spi register mapping: 0x82,0x83) seconda ry converter input [1] seconda ry lane output [1] seconda ry converter input [1] seconda ry lane output [1] jesd204b lane control (m = 1, 2; l = 1, 2) 10559-049 figure 54. ad9250 transmit link simplified block diagram
data sheet ad9250 rev. e | page 29 of 45 8b/10b encoder/ character replacement serializer t . . . ~sync sysref vina+ (msb) (lsb) vina? serdout a path adc test pattern 16-bit jesd204b test pattern 8-bit adc a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 c0 octet0 octet1 c1 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 e0 e1 e2 e3 e4 e5 e6 e7 e10 e11 e12 e13 e14 e15 e16 e17 e8 e9 e0e1e2 e3 e4e5e6 e7e8 e9 e18 e19 e19 optional scrambler 1 + x 14 + x 15 jesd204b test pattern 10-bit 10559-050 figure 55. ad9250 digital processing of jesd204b lanes table 13. ad9250 jesd204b typical configurations jesd204b configure setting m (no. of converters), register 0x71, bits[7:0] l (no. of lanes), register 0x6e, bit 0 f (octets/frame), register 0x6f, bits[7:0], read only s (samples/adc/frame), register 0x74, bits[4:0], read only hd (high density mode), register 0x75, bit 7, read only 0x11 1 1 2 1 0 0x12 1 2 1 1 1 0x21 2 1 4 1 0 0x22 (default) 2 2 2 1 0 data from adc frame assembler (add tail bits) optional scrambler 1 + x 14 + x 15 8b/10b encoder to receiver 10559-052 figure 56. ad9250 adc output data path
ad9250 data sheet rev. e | page 30 of 45 table 14. ad9250 jesd204b configuration, register 0x3a bit no. register description functional description 0 enable internal sy sref buffer this bit controls the on - chip buffer for the sysref singal. by default, this bit is 0, which disables the buffer. if the ad9250 is configured for jesd204b subclass 1 operation, sysref is required to align the jesd204b link and this bit must be set to 1. to avoid a false trigger as a result of transients caused when enabling the buffer (particularly for one - shot sysref configuration), set this bit first and then in a consecutive spi register write, configure all remaining bits in r egister 0x3a to the desired jesd204b link configuration , including keeping this bit at 1. a setting of 0 ( d efault) gate s the sysref signal such that the internal logic is not affected by an external sysre f. set t his bit to 0 when in subclass 0, that is, when sysref is not used. if using subclass 1 with one - shot sysref mode, enable the buffer while the sysref is established, but then disable it during normal operation. if using subclass 1 with continu ous sysref mode, the buffer must remain enabled for normal operation. 1 sysref enable this bit enable s the circuitry that uses the sysref input signal and must be on to enable subclass 1 operation. set t his bit to 1 when using jesd204b subclass 1 operati on. this bit is self clearing after a valid sysref occurs when sysref mode ( r egister 0x3a , bit 2) is set to 1 (configured for one - shot sysref operation). note that sysref is still used in some digital circuitry even if this bit is 0 ; to disable the sysref signal internally, register 0x3a bit 0 must be set to 0. 2 sysref mode this bit is used in subclass 1 operation to define o ne shot or continuous sysref mode. to configure continuous (or gapped periodic) sysref, this bit is set to 0. for one - shot operation, this bit is set to 1. in one - shot mode, it is recommended that the sysref buffer be disabled after sysref has occurred by setting register 0x3a , bit 0 to 0. 3 realign on sysref; f orsubclass 1 o nly when this bit is set to 1, the internal clock a lignment for the jesd204b timing is forced when an active sysref occurs. this is recommended only for one - shot mode and must only be done prior to initially establishing a link. this reset s the jesd204b link on active sysref . for continuous sysref mode, this bit must be set to 0 during normal operation. 4 realign on syncb; for subclass 1 o nly when this bit is set to 1, the internal clock alignment for the jesd204b timing is forced when an active sync occurs. an active sync requires the syncinb input to be logic low for at least four consecutive lmfc s . table 15. ad9250 jesd204b frame alignment monitoring and correction replacement characters scrambling lane synchronizat ion character to be replaced last octet in multiframe replacement character off on last octet in frame repeated from previous frame no k28.7 off on last octet in frame repeated from previous frame yes k28.3 off off last octet in frame repeated from pr evious frame not applicable k28.7 on on last octet in frame equals d28.7 no k28.7 on on last octet in frame equals d28.3 yes k28.3 on off last octet in frame equals d28.7 not applicable k28.7 frame and lane align ment monitoring and correction f rame alignment monitoring and correction is part of the jesd204b specification . the 14 - bit word requires two octets to transmit all the data. the two octets (msb and lsb), where f = 2, make up a frame. during normal operating conditions , frame alignment is monitored via alignment characters, which are inserted under certain conditions at the end of a frame. table 15 summarizes the conditions for character insertion along with the expected characters under the various operation mod es. if lane synchronization is enabled, the replacement character value depends on whether the octet is at the end of a frame or at the end of a multiframe. based on the operating mode, the receiver can ensure that it is still synchronized to the frame bo undary by correctly receiving the replacement characters. digital outputs and timing the ad9250 has differential digital outputs that power up by defaul t. t he driver current is derived on - chip and sets the output current at each output equal to a nominal 4 ma. each output presents a 100 ? dynamic internal termination to reduce unwanted reflections. place a 100 ? differential termination resistor at each receiver input to result in a nominal 3 00 mv peak - to - peak swing at the re ceiver (see figure 57 ). alternatively, single - ended 50 ? termination can be used. when single - ended termination is used, the termination voltage should be drvdd/2; otherwise, ac coupling capacitors can be used to terminate to any single - ended voltage. 100? or 100? differential trace pair serdoutx+ drvdd v rxcm serdoutx? v cm = rx v cm output swing = v od (see table 3) 0.1f 0.1f receiver 10559-053 figure 57 . ac - coupled digital output termination example
data sheet ad9250 rev. e | pag e 31 of 45 the ad9250 digital outputs can interface with custom asics and fpga receivers, providin g superior switching performance in noisy environments. single point - to - point network topologies are recommended with a single differential 100 ? termination resistor pl aced as close to the receiver logic as possible. the common mode of the digital output automatically biases itself to half the supply of the receiver (that is, the common - mode voltage is 0 .9 v for a receive r supply of 1.8 v) if dc - coupled connecting is used (see figure 58 ). for receiver logic that is not within the bounds of the drvdd supply, use an ac - coupled connection. simply place a 0.1 f capacitor on each ou tput pin and derive a 100 ? differential termination close to the receiver side. 100? 100? differentia l trace p air d r vdd v cm = d r vdd/2 receiver serdoutx+ serdoutx? 10559-054 output swing = v od (see table 3) figure 58 . dc - coupled digital output termination example if there is no far - end receiver termination , or if there is poor differential trace routing, timin g errors may result. to avoid such timing errors, it is recommended that the trace length be less than six inches , and that the differential output traces be close together and at equal lengths. figure 59 show s an example of the digital output (default) data eye and time interval error (tie) jitter histogram and bathtub curve for the ad9250 lane running at 5 gbps . additional spi options allow the user to further increas e the output driver voltage swing of all four outputs to drive longer trace lengths (see register 0x15 in table 18 ). t he power dissipation of the drvdd supply increases when this option is used. see the me mory map section for more details. the format of the output data is twos complement by default. to change the output data format to offset binary, see the memory map section (register 0x14 in table 18). 0 ? 0 . 5 0 . 5 uis pe r i o d 1 : h i s t o g r a m 6000 7000 ?10 0 time (ps) 10 5000 4000 1000 0 2000 3000 1 ?16 1 ?14 1 ?12 1 ?10 1 ?8 1 ?6 1 ?4 1 ?2 1 ber 3 ? 2 ? ?100 ?200 0 100 200 t i me (p s ) 400 300 200 100 0 ?100 ?300 ?400 ?200 voltage (mv) h e i g h t 1 : eye d i a g r a m 1 ? 10559 - 05 6 tj@ber1: b athtub hits ey e: transition bits offset: ?0.0072 uis: 8000; 999992 total: 8000.999992 0.78 ui figure 59. ad9250 digital outputs data eye, histogram and bathtub, external 100 ? terminations at 5 gbps 0 ? 0 . 5 0 . 5 uis pe r i o d 1 : h i s t o g r a m 4000 4500 ?10 0 time (ps) 10 3500 3000 1000 0 2000 2500 1500 500 1 ?16 1 ?14 1 ?12 1 ?10 1 ?8 1 ?6 1 ?4 1 ?2 1 ber 3 ? 2 ? ?250 ?150 0 50 ?50 150 250 t i me (p s ) 400 300 200 100 0 ?100 ?300 ?400 ?200 voltage (mv) h e i g h t 1 : eye d i a g r a m 1 ? 10559 - 15 6 tj@ber1: b athtub hits 0.84 ui ey e: transition bits offset: 0 uis: 8000; 679999 total: 8000; 679999 figure 60 . ad9250 digital outputs data eye, histogram and bathtub, external 100 terminations at 3.4 gbps
ad9250 data sheet rev. e | page 32 of 45 adc overrange and gain control in receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. the standard overflow indicator provides delayed information on the state of the analog input that is of limited value in preventing clipping. therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip occurs. in addition, because input signals can have significant slew rates, latency of this function is of concern. using the spi port, the user can provide a threshold above which the fd output is active. bit 0 of register 0x45 enables the fast detect feature. register 0x47 to register 0x4a allow the user to set the threshold levels. as long as the signal is below the selected threshold, the fd output remains low. in this mode, the magnitude of the data is considered in the calculation of the condition, but the sign of the data is not considered. the threshold detection responds identically to positive and negative signals outside the desired range (magnitude). adc overrange (or) the adc overrange indicator is asserted when an overrange is detected on the input of the adc. the overrange condition is determined at the output of the adc pipeline and, therefore, is subject to a latency of 36 adc clock cycles. an overrange at the input is indicated by this bit 36 clock cycles after it occurs. gain switching the ad9250 includes circuitry that is useful in applications either where large dynamic ranges exist, or where gain ranging amplifiers are employed. this circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. one such use is to detect when an adc is about to reach full scale with a particular input condition. the result is to provide an indicator that can be used to quickly insert an attenuator that prevents adc overdrive. fast threshold detection (fda and fdb) the fd indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located in register 0x47 and register 0x48. the selected threshold register is compared with the signal magnitude at the output of the adc. the fast upper threshold detection has a latency of 7 clock cycles. the approximate upper threshold magnitude is defined by upper threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 13 ) or, alternatively, the register value can be calculated by the target threshold using the following equation: value = 10 ( threshold magnitude [dbfs]/20) 2 13 the fd indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. the lower threshold is programmed in the fast detect lower threshold registers, located at register 0x49 and register 0x4a. the fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the adc. this comparison is subject to the adc pipeline latency but is accurate in terms of converter resolution. the lower threshold magnitude is defined by lower threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 13 ) for example, to set an upper threshold of ?6 dbfs, write 0x0fff to those registers; and to set a lower threshold of ?10 dbfs, write 0x0a1d to those registers. the dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located in regi ster 0x4b and register 0x4c. the operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in figure 61. upper threshold lower threshold fda or fdb midscale dwell time timer reset by rise above lt timer completes before signal rises above lt dwell time 10559-057 figure 61. threshold settings for fda and fdb signals
data sheet ad9250 rev. e | pag e 33 of 45 dc c orrection because the dc offset of the adc may be significantly larger than the signal being measured, a dc correction circuit i s included to null the dc offset before measuring the power. the dc correction circuit can also be switched into the main signal path ; however, this may not be appropriate if the adc is digitizing a time - varying signal with significant dc content, such as gsm. dc correction bandwi dth the dc correction circuit is a high - pass filter with a program - mable bandwidth (ranging b etween 0.29 hz and 2.387 khz at 245.76 msps). the bandwidth is controlled by writing to the 4 - bit dc correction bandwidth select registe r, located at register 0x40, bits[5:2]. the fo llowing equation can be used to compute the bandwidth value for the dc correction circuit: dc_corr_bw = 2 ? k ?14 f clk /(2 ) where: k is the 4 - bit value programmed in bits[5:2] of register 0x40 (values betwee n 0 and 13 are valid for k ). f clk is the ad9250 adc sample rate in hertz. dc correction readba ck the current dc correction value can be read back in register 0x41 and register 0x42 for each chan nel. the dc correction value is a 16- bit value that can span the entire input range of the adc. dc correction freeze setting bit 6 of register 0x40 freezes the dc correction at its current state and continues to use the last updated value as the dc corre ction value. clearing this bit restarts dc correction and adds the currently calculated value to the data. dc correction (dcc) enable bits setting bit 1 of register 0x40 enables dc correction for use in the output data signal path.
ad9250 data sheet rev. e | page 34 of 45 serial port in terface (spi) the ad9250 spi allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user ad ded flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the memory map section. for detailed operational information , see the an - 877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin , the sdio pin , and the cs pin (s ee table 16 ). the sclk (serial clock) pin is used to synchronize the read and write d ata presented from/to the adc. the sdio (s eri al data input/output) pin is a dual - purpose pin that allows data to be sent and read from the internal adc memory map registers. the cs (chip select bar) pin is an active low control that enables or disab les the read and write cycles. table 16. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface , reads and writes. sdio serial data input/output. a dual - purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. cs chip select bar. an active low control that gates the read and write cycles. the falling edge of cs , in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 62 and table 5 . other modes involvi ng the cs are available. the cs can be held low indefinitely, which permanently enables the device; this is called streaming. the cs can stall high between bytes to allow for additional external timing. when cs is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16 - bit instruction is transmitted. data follows the instruction phase, and its l ength is determined by the w0 and the w1 bit s. all data is composed of 8 - bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the sdio pin to change direction from an input t o an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb f irst mode. msb first is the default on power - up a nd can be changed via the spi port configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . hardware int erface the pins described in table 16 comp ri se the physical interface between the user programming device and the serial port of the ad9250 . the sclk pin and the cs pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microco n trollers. one method for spi configuration is described in detail in the an - 812 application note , microcontroller - based serial port interface (spi) boot circuit . do not activate t he spi port duri ng periods when the full dynamic performance of the converter is required. because the sclk signal, the cs signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance . if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9250 to prevent these signals from transitioning at the converter inputs duri ng critical sampling periods.
data sheet ad9250 rev. e | pag e 35 of 45 spi accessible featu res table 17 provides a brief description of the general features that are accessible vi a the spi. these features are described in detail in the an - 877 application note , interfacing to high speed adcs via spi . the ad9250 part - specific features are described in the memory map re gister description section . table 17 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs via the spi offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output de lay allows the user to vary the dco delay vref allows the user to set the reference voltage don?t care don?t care don?t care don?t care sdio sclk cs t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 10559-058 figure 62 . serial port interface timing diagram
ad9250 data sheet rev. e | page 36 of 45 m emory ma p reading the memory m ap register table each row in the memory map register table has eight bit locations. the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0x05 and address 0xff); and the adc functions register s, including setup, control, and te st (address 0x08 to address 0x a8 ). the memory map register table (see table 18 ) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (ms b) is the start of the default hexadecimal value given. for example, address 0x1 4 , the output mode register, has a h exadecimal default value of 0x0 1 . this means that bit 0 = 1 , and the remaining bits are 0s. this setting is the default output format value , which is twos compl e ment . for more information on this function and others, see the an - 877 application note , interfacing to high speed adcs via spi . this document details the functions controlled by register 0x00 to register 0x 25 . the remaining registers, re gister 0 x3a and register 0x 59 , are documented in th e memory map register description section. open and reserved locations all address and bit locations that are not included in table 18 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for exampl e, address 0x18). if the entire address location is open (for example, address 0x13), do not write to this address location. default values after the ad9250 is reset, critical registers are loade d with default values. the default values for the registers are given in the memory map register table, table 18. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to lo gic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel - specific registers some channel setup functions, such as dc offset adjust or ouput data format , can be programmed t o a different value for each channel. in these cases, channel address locations are internally duplicated or shadowed for each chann el. these registers and bits are designated as local in table 18 . n ote that all other li sted registers are considered as global ; write operations to these registers affect the entire device upon completion of the write operation. l ocal registers and bits can be accessed by setting the appropriate channel a or channel b bits in regis ter 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, set only channel a or channel b to read one of the two registers. if both bits are set during an spi read cycle, the device r eturns the value for channel a. to write to a specific channel, the following three steps must occur: 1. select the desired channel(s) for spi write operation via register 0x05. 2. perform the specific write operation to desired local spi register. 3. transfer of the write operation co ntents to the target local register occurs by setting the self clearing transfer bit of r egister 0xff. writing 0x01 allows the target local channel register(s) to be updated internally and simultaneously when the transfer bit is set. the internal update ta kes place when the transfer bit is set and then the bit auto matically clears.
data sheet ad9250 rev. e | pag e 37 of 45 memory map register table all address and bit locations that are not included in table 18 are not currently supported for this device. table 18 . memory map registers reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x00 global spi c onfig 0 lsb f irst soft r eset 1 1 soft r eset lsb f irst 0 0x18 0x01 chip id ad9250 8 - bit chip id is 0xb9 0xb9 read o nly 0x02 chip i nfo speed g rade 00 = 250 msps 11 = 170 msps reserved for chip die revision currently 0x0 0x00 o r 0x30 0x05 channel i ndex spi w rite t o adc b p ath s pi write to adc a p ath 0x03 0x08 pdwn m odes external pdwn m ode ; 0 = pdwn is full power down ; 1 = pdwn puts device in standby jtx in s t an dby ; 0 = jesd 204b core is unaffected in s t an dby ; 1 = jesd 204b core is powered down except for pll during standby je sd204b power modes ; 00 = normal m ode (power up) ; 01 = power - down mode : pll off, s erializer off, clocks stopped, digital held in reset ; 10 = standby m ode: pll on, s erializer off, clocks stopped, digital held in reset chip power modes ; 00 = normal mode (powe r up) ; 01 = power - down mode, digital data path clocks disabled , digital datapath held in reset; most analog paths powered off ; 10 = standby m ode; digital datapath clocks disabled , digital datapath held in reset , some analog paths powered off (local) 0x00 0x09 global c lock (local) r eserved clock s election: 00 = nyquist c lock 10 = rf c lock divide by 4 11 = clock off clock duty cycle stabilizer (dcs) enable 0x01 local, dcs enabled if c lock divider enabled 0x0a pll s tatus pll locked status jesd 204 b l ink is ready read o nly 0x0b global clock divider (local) clock divide r phase output of the internal d ivide by 1 to d ivide by 8 divider circuit, clock cycles are relative to the input c lock to this block ; 0x0 = 0 input clock cycles delayed ; 0x1 = 1 i nput clock cycles delayed ; 0x2 = 2 input clock cycles delayed ; 0x7 = 7 input clock cycles delayed note that the rf c lock divider phase is not selectable clock divider ratio of the d ivide by 1 to d ivide by 8 divider circuit to generate the encode clock ; 0 x00 = d ivide by 1 ; 0x01 = d ivide by 2 ; 0x02 = d ivide by 3 ; 0x7 = d ivide by 8 ; u sing a clkdiv_divide_ratio > 0 (divide ratio > 1) cause s the dcs to be automatically enabled 0x00 local 0x0d test control reg (local) u ser test mode cycle ; 00 = repeat patte rn (u ser pattern 1, 2, 3, 4, 1, 2, 3, 4 , 1, ) ; 10 = s ingle pattern (u ser pattern 1, 2, 3, 4, then all zeros) long psuedo random number generator reset; 0 = l ong prn enabled ; 1 = l ong prn held in reset short psuedo random number generator reset; 0 = s hort prn enabled ; 1 = s hort prn held in reset data output test generation mode; 0000 = off (normal mode ) ; 0001 = m idscale short ; 0010 = p ositive f ull scale ; 0011 = n egative full scale ; 0100 = alternating checkerboard ; 0101 = pn 23 s equence l ong ; 0110 = pn 9 s equence s hort ; 0111 = one - / zero - word toggle ; 1000 = user test mode (use with reg ister 0x0d , b it 7 and u ser pattern 1, 2, 3, 4) ; 1001 to 1110 = u nused ; 1111 = ramp output 0x00 local
ad9250 data sheet rev. e | page 38 of 45 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x10 customer o ffset (local) offset a djust in lsbs from +31 to ? 32 (twos complement format) ; 01 1111 = a djust output by +31 ; 01 1110 = a djust output by +30 ; 00 0001 = a djust output by +1 ; 00 0000 = a djust output by 0 (default) ; 10 0001 = a djust output by ? 31 ; 10 0000 = a dju s t output by ? 32 0x00 local 0x14 o utput m ode (local) jtx cs bits assignment (in conjunction with reg ister 0x72) 000 = (o verrange|| u nderrange, v alid ) 001 = (o verrange|| u nderrange ) 010 = (o verrange|| u nderrange, b lank ) 011 = ( blank, valid ) 100 = ( blank, blank ) all others = ( o verrange|| u nderra nge, v alid ) disable output from adc invert adc data ; 0 = n ormal (default) ; 1 = i nverted digital datapath output data format select (dfs) (local) ; 00 = o ffset b inary ; 01 = twos complement 0x01 local 0x15 cml output adjust jesd204b cml differential o utput drive level adjustment; 000 = 81% of nominal (that is, 478 mv); 001 = 89% of nominal (that is, 526 mv); 010 = 98% of nominal (that is, 574 mv); 011 = nominal (default) (that is, 588 mv); 110 = 126% of nominal (that is, 738 mv) 0x03 0x18 adc vre f main reference full - scale vref adjustment; 0 1111 = internal 2.087 v p - p; 0 0001 = internal 1.772 v p - p; 0 0000 = internal 1.75 v p - p ( default ); 1 1111 = internal 1.727 v p - p; 1 0000 = internal 1.383 v p - p 0x00 local 0x19 user test pattern 1 l us er test pattern 1 lsb; use in conjunction with register 0x0d and register 0x61 0x00 0x1a user test pattern 1 m user test pattern 1 msb 0x00 0x1b user test pattern 2 l user test pattern 2 lsb 0x00 0x1c user test pattern 2 m user test pattern 2 msb 0x0 0 0x1d user test pattern 3 l user test pattern 3 lsb 0x00 0x1e user test pattern 3 m user test pattern 3 msb 0x00 0x1f user test pattern 4 l user test pattern 4 lsb 0x00 0x20 user test pattern 4 m user test pattern 4 msb 0x00 0x21 pll low encode 00 = for lane speeds > 2 gbps; 01 = for lane speeds < 2 gbps 0x00
data sheet ad9250 rev. e | pag e 39 of 45 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x3a syncinb/ sysref ctrl (local) syncinb operation 0 = normal mode; 1 = realign lanes on every active syncinb for subclass 1 only: 0 = normal mode; 1 = realign lanes on every active sysref ; use with single shot sysref in subclass 1 mode sysref m ode; 0 = c ontinuous reset clock dividers; 1 = s ync on next sysref rising edge only sysref enable; 0 = disabled; 1 = enabled . note: this bit self - clears after sysref if sysref mode = 1 enable internal sy sref buffer; 0 = buffer dis abled , external sysref pin ignored ; 1 = buffer en abled , use external sysref pin 0x00 local see table 14 for more details 0x40 dcc ctrl (local) freeze dc corr ection; 0 = calculate; 1 = freezeval dc correction bandwidth select; correction bandwidth is 2387.32 hz/reg val; there are 14 possible values; 0000 = 2387.32 hz; 0001 = 1193.66 hz; 1101 = 0.29 hz enable dcc 0x00 local 0x41 dcc value lsb (local) dc corre ction value[7:0] 0x00 local 0x42 dcc value msb (local) dc correction value[15:8] 0x00 local 0x45 fast detect control (local) pin f unction; 0 = fast detect; 1 = o verrange force fda/fdb p ins; 0 = normal function; 1 = force to value force value of fda/f db pins if f orce pins is true, this value is output on fd p in s enable fast detect output 0x00 local 0x47 fd upper threshold (local) fast detect upper threshold[7:0] 0x00 local 0x48 fd upper threshold (local) fast detect upper threshold[1 4 :8] 0x00 local 0x49 fd lower threshold (local) fast detect lower threshold[7:0] 0x00 local 0x4a fd lower threshold (local) fast detect lower threshold[1 4 :8] 0x00 local 0x4b fd dwell time (local) fast detect dwell time[7:0] 0x00 local 0x4c fd dwell time (local) fast detect dwell time[15:8] 0x00 local 0x5e 204b quick config quick configuration register, always reads back 0x00; 0x11 = m = 1, l = 1; one converter, one lane; second converter is not automatically powered down; 0x12 = m = 1, l = 2; one converter, two la nes; second converter is not automatically powered down; 0x21 = m = 2, l = 1; two converters, one lane; 0x22 = m = 2, l = 2; two converters, two lanes 0x00 always reads back 0x00
ad9250 data sheet rev. e | page 40 of 45 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x5f 204b link ctrl 1 tail bits: if cs bits are not enabled; 0 = extra bi ts are 0; 1 = extra bits are 9 - bit pn jesd204b test sample enabled reserved; set to 1 ilas mode; 01 = ilas normal mode enabled; 11 = ilas always on, test mode reserved; set to 0 power - down jesd204b link; set high while configuring link parameters 0x14 0x60 204b link ctrl 2 reserved; set to 0 reserved; set to 0 reserved; set to 0 invert logic of jesd204b bits 0x00 0x61 204b link ctrl 3 reserved; set to 0 reserved; set to 0 test data injection point; 01 = 10 - bit data at 8 b /10 b output; 10 = 8 - bit d ata at scrambler input jesd204b test mode patterns; 0000 = normal operation (test mode disabled); 0001 = alternating checker board; 0010 = 1/0 word toggle; 0011 = pn sequence pn23; 0100 = pn sequence pn9; 0101= continuous/repeat user test mode; 0110 = single user test mode; 0111 = reserved; 1000 = modified rpat test sequence, must be used with jtx_test_gen_sel = 01 (output of 8b/10b); 1100 = pn sequence pn7; 1101 = pn sequence pn15; other setting are unused 0x00 0x62 204b link ctrl 4 reserved 0x00 0x63 204b link ctrl 5 reserved 0x00 0x64 204b did config jesd204b did value 0x00 0x65 204b bid config jesd204b bid value 0x00 0x6 6 204b lid config 0 lane 0 lid value 0x00 0x6 7 204b lid config 1 lane 1 lid value 0x01 0x6e 204b parameters scr/l jesd204b scrambling (scr); 0 = disabled; 1 = enabled jesd204b lanes (l); 0 = 1 lane; 1 = 2 lanes 0x81 0x6f 204b parameters f jesd204b number of octets per frame (f); calculated value (note that this value is in x ? 1 forma t ) 0x01 read only 0x70 204b parameters k jesd204b number of frames per multiframe (k); set value of k per jesd204b specifications, but also must be a multiple of 4 octets (note that this value is in x ? 1 format ) 0x1f 0x71 204b parameters m jesd204b num ber of converters (m); 0 = 1 converter; 1 = 2 converters 0x01 0x72 204b parameters cs/n number of control bits (cs); 00 = no control bits (cs = 0); 01 = 1 control bit (cs = 1); 10 = 2 control bits (cs = 2) adc converter resolution (n), 0xd = 1 4 - bit converter (n = 14) (note that this value is in x ? 1 format ) 0x0d
data sheet ad9250 rev. e | pag e 41 of 45 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x73 204b parameters subclass/np jesd204b subclass; 0x0 = subclass 0; 0x1 = subclass 1 (default) jesd204b n value; 0xf = n = 16 (note that this value is in x C 1 format ) 0x2f 0x74 204b parameters s reserved; set to 1 jesd204b s amples per converter frame cycle (s); read only (note that this value is in x ? 1 format) 0x20 0x75 204b parameters hd and cf jesd204b hd value; read only jesd204b control words per frame clock cycle per link (cf); read only 0x00 read only 0x76 204b resv1 reserved field number 1 0x00 0x77 204b resv2 reserved field number 2 0x00 0x7 8 204b chksum0 jesd204b serial checksumvalue for lane 0 0x42 0x7 9 204b chksum1 jesd204b serial checksumvalue for lane 1 0x43 0x82 204b lane assign 1 00 = assign lo gical lane 0 to physical lane a (default) ; 01 = assign logical lane 0 to physical lane b reserved; set to 1 reserved; set to 0 0x02 0x83 204b lane assign 2 reserved; set to 1 reserved; set to 1 00 = assign logical lane 1 to physical lane a; 01 = assign logical lane 1 to physical lane b (default) 0x31 0x8b 204b lmfc offset local multiframe clock (lmfc) phase offset value; reset value for lmfc phase counter when sysref is asserted; used for deterministic delay applications 0x00 0xa8 204b pre - emphasis jesd204b pre - emphasis enable option (consult factory for more detail); set value to 0x04 for pre - emphasis off; set value to 0x14 for pre - emphasis on 0x04 typically not required 0xee internal d igital c lock d elay enable i nternal c lock d elay set to 0 set to 0 set to 0 use incrementing values from 0 to 7 to increase internal digital clock delay. for internal data latching purposes, this does not affect external timing. 0x00 see jesd section for use 0xef internal d igital c lock d elay enable i nternal c lock d elay set to 0 set to 0 set to 0 use incrementing values from 0 to 7 to increase internal digital clock delay. for internal data latching purposes, this does not affect external timing. 0x00 see jesd section for use 0xf3 internal d igital c lock a lig nment force manual re - align on lane 1, self clearing lane 1 alignment complete force manual realign on lane 0, s elf clearing lane 0 a lignment complete 0x14 see jesd section for use 0xff device update (global) transfer s ettings memory map register description for more informat ion on functions controlled in register 0x00 to register 0x 25 , see the an - 877 application note , interfacing to high speed adcs via spi .
ad9250 data sheet rev. e | page 42 of 45 applications inform ation design guidelines before starting system level de sign and layout of the ad9250 , it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the ad9250 , use two separate 1.8 v power supplies . t he power supply for avdd can be isolated and for dvdd and drvdd it can be tied together, in which case isolation between dvdd and drvdd is required. isolation can be achieved using a ferrite bead or an inductor of approximately 1 h. an unfiltered switching regulator is not recomm ended for the drvdd supply as it impacts the performance of the jesd204 b serial transmission lines and may result in link problems. alternate - ly, the jesd204b phy power (drvdd) and analog (avdd) supplies can be tied together , and a separate supply can be u sed for the digital outputs (dvdd). the designer can employ several different decoupling capacitors to cover both high and low frequencies. locate t hese capacitors close to the point of entry at the pc board level and close to the pins of the part with mi nimal trace length . each power supply domain must have local high frequency decoupling capacitors. this is especially important for drvdd and avdd to maintain analog performance. when using the ad9 250, a single pcb ground plane should be sufficient. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is mandatory tha t the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. mate a continuous, exposed (no solder mask) copper plane on the pcb to the ad9250 exposed paddle, pin 0. the copper plane must have several vias to achieve the lowest pos - sibl e resistive thermal path for heat dissipation to flow through the bottom of the pcb. fill or plug these vias with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, overlay a silkscreen to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. usi ng one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about the packaging and pcb layout of chip scale packages, refer to the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . vcm decouple t he vcm pin to ground with a 0.1 f capacitor, as shown in figure 40. for optimal channel - to - channel isolation, include a 33 ? resistor between the ad9250 vcm pin and the channel a analog input network connection , as well as between the ad9250 vcm pin and the channel b analog input network connection. spi port when the full dynamic performance of the converter is required , do not activate t he spi port during periods. because the sclk, cs , and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance . if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9250 to keep these signals from transitioning at the converter input pins d uring critical sampling periods. spi initialization s equence on power - up of the ad9250 , a host processor is required to initialize and configure the ad9250 via its spi port. figure 63 shows a flowchart of the sequential steps required to bring the ad9250 to an operational state. the number of spi writes and total initialization time is dependent on how many spi registers need to be changed from the default settin g, usage of the clock divider , and whether jesd204b subclass 1 sync h r onization is required . table 19 shows the minimum spi writes required to enable the ad9250 . note the following in the sequence of steps shown in table 19: ? steps that are listed as optional can be ignored if the default spi settings are sufficient. ? steps that are listed as c onditio n al can be ignored if the specif ic condition is no t applicable.
data sheet ad9250 rev. e | pag e 43 of 45 set the quick jesd204 configuration mode (refer to table 13) reset internal clocks to minimum setting fifo write/read clock adjustment wait >6lmfc clocks optional modify any other jesd204b parameters from default setting disable the jesd204b txphy during set-up (as well as jesd204b rx) apply power and clock allow time to settle issue software reset then wait 500s min issue software power-down set divider value optional configure any non-jesd204 registers from default setting use clock divider? yes no issue software power-up wait 250ms use clock divider? yes no jesd204b subclass1 sync yes no enable sysref buffer configure sysref mode readbackpll lock bit enable phy to begin cgs phase force fifo alignment wait >6lmfc clocks apply external sysref wait >6lmfc clocks disable sysref buffer (one-shot mode only) jesd204b subclass1 sync yes no 10559-063 figure 63 . flow chart showing sequence of steps required to initialize the ad9250 table 19. spi initialization sequence step addre ss write value comments 1 apply power to the ad9250 and allow the voltages and clocks to stabilize. 2 0x00 0x3c software reset. 3 wait 500 s minimum. 4 0x5f 0x15 disable the jesd204b phy. 5 optional: m odify any other non - jesd204b register from default setting depending on application requirements. note, any local register must be followed by a transfer command (0xff= 0x01) 6 0x0b 0x01 optional: s et the clock divider ratio if using a c lock divider. note that the 0x01 value shown corresponds to a divide -by - 2 clock ratio . 0xff 0x01 transfer command for l ocal register 7 0x5e 0xml set the jesd204b quick configuration reg ister based on the desired m and l values . 8 0xee 0x80 enable the i nternal clock delay block for minimum delay . 9 0x21 0x00 conditional: c onf igure the pll low encode register. only set to 0 x01 if the lane rate is < 2 gbps. the d efault setting is 0x00 . 10 optional: modify the jesd204b centric registers from the default setting as follows: 0x14 0x01 configure the data output with 0x01 being the default (twos complement). 0x15 0x03 set the jesd204b cml differential drive level with 0x03 being default (588 mv). 0x66 0x00 set the lane 0 and lane 1 lid value (defaults shown). 0x67 0x01 set the lane 0 and lane 1 lid value (defaults shown). 0x6e 0x81 enable the jesd204b scrambling in bit 7 while keeping desired jesd204b lane value, l, in bit 0. default shown. 0x70 0x1f modify the jesd204b k and cs values. default sh own. 0x82 0x0d modify the jesd204b k and cs values. default shown. modify other jesd204b centric configurations in register 0x82 to register 0x8b and register 0xa8. 0xff 0x01 transfer command for local register
ad9250 data sheet rev. e | page 44 of 45 step addre ss write value comments 11 optional: jesd204b subclass 1 synchronization set up . 0x3a 0x01 enable the sysref buffer first to avoid f alse triggering (especially one - shot operation) before setting the remaining bits in register 0x3a. 0xff 0x01 transfer command for local register 0x3a 0x0f or 0x03 configure th e method of sysref operation. for one - shot operation, set to 0x0f. for continuous or gapped periodic sysref operation, set to 0x03. 0xff 0x01 transfer command for local register 12 begin jesd204b link establishment. 0x0a optional: read back registe r 0x0a with 0x81 indicating that the jesd204b pll is locked. 0x5f 0x14 enable the jesd204b phy. this begins the cgs phase for establishing a link. 0xf3 0xff force an internal fifo alignment. wait at least six lmfc cycles. note that the jesd204b link must be established at this time before continuing. 13 optional: when operating in subclass 1 mode, apply external sysref signal for lmfc alignment. wait at least six lmfc cycles for lmfc alignment between jesd204b tx and rx to occur. 0x3a 0x04 conditional: disable the internal sysref buffer if configured for one - shot operation. 0xff 0x01 transfer command for local register 14 internal fifo clock a djustment . 0xee 0x81 clock adjustment p rocedure . 1 0xef 0x81 clock adjustment p rocedure . 1 0xee 0x82 clock adjustment p rocedure . 1 0xef 0x82 clock a djust ment p rocedure . 1 0xee 0x83 clock adjustment p rocedure . 1 0xef 0x83 clock adjustment p rocedure . 1 0xee 0x84 clock adjustment p rocedure . 1 0xef 0x84 clock adjustment p rocedure . 1 0xee 0x85 clock adjustment p ro cedure . 1 0xef 0x85 clock adjustment p rocedure . 1 0xee 0x86 clock adjustment p rocedure . 1 0xef 0x86 clock adjustment p rocedure . 1 0xee 0x87 clock adjustment p rocedure . 1 0xef 0x87 clock adjustment p rocedure . 1 wait at least six lmfc cycles . 1 following this procedure optimizes write and read clock delays of internal fifo to avoid possible overflow, over temperature , and supply varia tions.
data sheet ad9250 rev. e | page 45 of 45 outline dimensions compliant to jedec standards mo-220-wkkd-4. 1 0.50 bsc bottom view top view pin 1 indicator 48 13 24 36 37 5.70 5.60 sq 5.50 0.50 0.40 0.30 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 02-29-2016-a 7.10 7.00 sq 6.90 0.20 min 5.50 ref end view exposed pad pkg-004452 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. p i n 1 i n d i c a t o r a r e a o p t i o n s ( s e e d e t a i l a ) detail a (jedec 95) seating plane figure 64. 48-lead lead frame chip scale package [lfcsp] 7 mm 7 mm body and 0.75 mm package height (cp-48-13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9250bcpz-170 ?40c to +85c 48-lead lead frame chip scale package [lfcsp] cp-48-13 ad9250bcpzrl7-170 ?40c to +85c 48-lead lead frame chip scale package [lfcsp] cp-48-13 AD9250-170EBZ ?40c to +85c eval uation board with ad9250-170 ad9250bcpz-250 ?40c to +85c 48-lead lead frame chip scale package [lfcsp] cp-48-13 ad9250bcpzrl7-250 ?40c to +85c 48-lead lead frame chip scale package [lfcsp] cp-48-13 ad9250-250ebz ?40c to +85c eval uation board with ad9250-250 1 z = rohs compliant part. ?2012C2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10559-0-9/17(e)

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